Bambino-100 Manual/Hardware - Revision history

Support: /* ESP12 WiFi Module Option */

Support — Wed, 02 Mar 2016 20:56:08 GMT

ESP12 WiFi Module Option

← Older revision		Revision as of 20:56, 2 March 2016
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	==ESP12 WiFi Module Option==		==ESP12 WiFi Module Option==
-		+	The ESP12 is a WiFi module based on the ESP8266 processor from Espressif. It is a microcontroller with a WiFi front-end and TCP/IP stack with DNS support. The ESP12 can be populated on the bottom of the Bambino 100.

	==MBED HDK Option==		==MBED HDK Option==

Support: /* LPC4337 key features */

Support — Tue, 23 Feb 2016 15:38:24 GMT

LPC4337 key features

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	* Clock generation unit		* Clock generation unit
	** Crystal oscillator with an operating range of 1 MHz to 25 MHz.		** Crystal oscillator with an operating range of 1 MHz to 25 MHz.
-	** 12 MHz internal RC oscillator trimmed to 3 % accuracy over temperature and	+	** 12 MHz internal RC oscillator trimmed to 3 % accuracy over temperature and voltage (1.5 % accuracy for Tamb = 0 °C to 85 °C).
-	voltage (1.5 % accuracy for Tamb = 0 °C to 85 °C).	+
	** Ultra-low power Real-Time Clock (RTC) crystal oscillator.		** Ultra-low power Real-Time Clock (RTC) crystal oscillator.
	** Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used with the High-speed USB, the third PLL can be used as audio PLL.		** Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used with the High-speed USB, the third PLL can be used as audio PLL.

Support: /* LPC4337 key features */

Support — Tue, 23 Feb 2016 15:37:24 GMT

LPC4337 key features

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	** Two I2S interfaces, each with DMA support and with one input and one output.		** Two I2S interfaces, each with DMA support and with one input and one output.
	* Digital peripherals		* Digital peripherals
-	** External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,	+	** External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.
-	and SDRAM devices.	+
	** Secure Digital Input Output (SD/MMC) card interface.		** Secure Digital Input Output (SD/MMC) card interface.
	** Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves.		** Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves.
-	** Up to 164 General-Purpose Input/Output (GPIO) pins with configurable	+	** Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors.
-	pull-up/pull-down resistors.	+
	** GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.		** GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
	** Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.		** Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.
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	* Analog peripherals		* Analog peripherals
	** One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.		** One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
-	** Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.	+	** Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight input channels per ADC.
-	Up to eight input channels per ADC.	+
	* Unique ID for each device.		* Unique ID for each device.
	* Clock generation unit		* Clock generation unit

Support: /* LPC4337 key features */

Support — Tue, 23 Feb 2016 15:35:56 GMT

LPC4337 key features

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	** 16 kB on-chip EEPROM data memory.		** 16 kB on-chip EEPROM data memory.
	** 136 kB SRAM for code and data use.		** 136 kB SRAM for code and data use.
-	** Multiple SRAM blocks with separate bus access. Two SRAM blocks can be	+	** Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually.
-	powered down individually.	+
	** 64 kB ROM containing boot code and on-chip software drivers.		** 64 kB ROM containing boot code and on-chip software drivers.
	** 64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose use.		** 64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose use.

Support: /* LPC4337 key features */

Support — Tue, 23 Feb 2016 15:35:18 GMT

LPC4337 key features

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	powered down individually.		powered down individually.
	** 64 kB ROM containing boot code and on-chip software drivers.		** 64 kB ROM containing boot code and on-chip software drivers.
-	** 64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose	+	** 64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose use.
-	use.	+
	* Configurable digital peripherals		* Configurable digital peripherals
	** Serial GPIO (SGPIO) interface.		** Serial GPIO (SGPIO) interface.
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	** Brownout detect with four separate thresholds for interrupt and forced reset.		** Brownout detect with four separate thresholds for interrupt and forced reset.
	** Power-On Reset (POR).		** Power-On Reset (POR).
-

	===LPC4337 Block Diagram===		===LPC4337 Block Diagram===

Support at 14:51, 23 February 2016

Support — Tue, 23 Feb 2016 14:51:14 GMT

← Older revision		Revision as of 14:51, 23 February 2016
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	The following image shows where some of the hardware components are located.		The following image shows where some of the hardware components are located.

-	[[Image:Bambino-~~210~~-Hardware.png\|center\|alt=Bambino ~~210~~ Hardware Diagram\|frame\|<div align="center">'''Bambino ~~210~~ Hardware]]	+	[[Image:Bambino-100-Hardware.png\|center\|alt=Bambino 100 Hardware Diagram\|frame\|<div align="center">'''Bambino 100 Hardware]]
	</div>		</div>
	==Microcontroller==		==Microcontroller==

Support: Created page with '4 The following image shows where some of the hardware components are located. [[Image:Bambino-210-Hardware.png|center|alt=Bambino 210 Hardware …'

Support — Tue, 23 Feb 2016 14:50:15 GMT

Created page with '4 The following image shows where some of the hardware components are located. [[Image:Bambino-210-Hardware.png|center|alt=Bambino 210 Hardware …'

New page

[[Category: Bambino-100_Manual|4]]
The following image shows where some of the hardware components are located.

[[Image:Bambino-210-Hardware.png|center|alt=Bambino 210 Hardware Diagram|frame|<div align="center">'''Bambino 210 Hardware]]
</div>
==Microcontroller==
The Bambino 100 includes a NXP LPC4337 microcontroller. These dual core 32-bit ARM Cortex-M4/M0 RISC microcontroller are capable of 204-MHz operation with a Thumb2 instruction set for smaller object code. It uses a Harvard architecture with separate local instruction and data buses as well as a separate peripherals bus. Please see NXP’s LPC4337 Microcontroller's User Manual for more information and register definitions.

===LPC4337 key features===
*Cortex-M4 Processor core
** ARM Cortex-M4 processor (version r0p1), running at frequencies of up to 204 MHz.
** Built-in Memory Protection Unit (MPU) supporting eight regions.
** Built-in Nested Vectored Interrupt Controller (NVIC).
** Hardware floating-point unit.
** Non-maskable Interrupt (NMI) input.
** JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.
** Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
** System tick timer.
* Cortex-M0 Processor core
** ARM Cortex-M0 co-processor (version r0p0) capable of off-loading the main ARM Cortex-M4 application processor.
** Running at frequencies of up to 204 MHz.
** JTAG
** Built-in NVIC.
* On-chip memory
** Up to 1 MB on-chip dual bank flash memory with flash accelerator.
** 16 kB on-chip EEPROM data memory.
** 136 kB SRAM for code and data use.
** Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
** 64 kB ROM containing boot code and on-chip software drivers.
** 64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose
use.
* Configurable digital peripherals
** Serial GPIO (SGPIO) interface.
** State Configurable Timer (SCTimer/PWM) subsystem on AHB.
** Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.
* Serial interfaces
** Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.
** 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).
** One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY.
** One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY.
** USB interface electrical test software included in ROM USB stack.
** One 550 UART with DMA support and full modem interface.
** Three 550 USARTs with DMA and synchronous mode support and a smart card interface conforming to ISO7816 specification. One USART with IrDA interface.
** Up to two C_CAN 2.0B controllers with one channel each.
** Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.
** One SPI controller.
** One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.
** One standard I2C-bus interface with monitor mode and with standard I/O pins.
** Two I2S interfaces, each with DMA support and with one input and one output.
* Digital peripherals
** External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
** Secure Digital Input Output (SD/MMC) card interface.
** Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves.
** Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors.
** GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
** Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.
** Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
** Four general-purpose timer/counters with capture and match capabilities.
** One motor control Pulse Width Modulator (PWM) for three-phase motor control.
** One Quadrature Encoder Interface (QEI).
** Repetitive Interrupt timer (RI timer).
** Windowed watchdog timer (WWDT).
** Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.
** Alarm timer; can be battery powered.
* Analog peripherals
** One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
** Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
Up to eight input channels per ADC.
* Unique ID for each device.
* Clock generation unit
** Crystal oscillator with an operating range of 1 MHz to 25 MHz.
** 12 MHz internal RC oscillator trimmed to 3 % accuracy over temperature and
voltage (1.5 % accuracy for Tamb = 0 °C to 85 °C).
** Ultra-low power Real-Time Clock (RTC) crystal oscillator.
** Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used with the High-speed USB, the third PLL can be used as audio PLL.
** Clock output.
* Power
** Single 3.3 V (2.4 V to 3.6 V) power supply with on-chip DC-to-DC converter for the core supply and the RTC power domain.
** RTC power domain can be powered separately by a 3 V battery supply.
** Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
** Processor wake-up from Sleep mode via wake-up interrupts from various peripherals. Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.
** Brownout detect with four separate thresholds for interrupt and forced reset.
** Power-On Reset (POR).

===LPC4337 Block Diagram===
[[Image:Bambino-100-MCUBlock.png|center|alt=LPC4337 Block Diagram|frame|<div align="center">'''LPC4337 Block Diagram]]
</div>

===LPC4337 Memory Map===
[[Image:Bambino-100-Mem-Map.png|center|alt=LPC4337 Memory Map|frame|<div align="center">'''LPC4337 Memory Map]]
</div>

==ESP12 WiFi Module Option==

==MBED HDK Option==
The MBED HDK is powered by NXP's LPC11U35. The mbed HDK uses the CMSIS-DAP Interface design that provides simple USB drag-n-drop programming and CMSIS-DAP debug interface for the target microcontroller.

==Serial Flash Memory Option==
The Bambino 100 has an optional Quad SPI Flash for program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz.

----

[[Bambino-100_Manual/User Interfaces, Connectors, and Jumpers|NEXT: User Interfaces, Connectors, and Jumpers]]

[[Bambino-100_Manual/Rebuild Firmware|PREVIOUS: Rebuild Firmware]]