Using CPLD/1 - Revision history

Support at 14:55, 21 June 2010

Support — Mon, 21 Jun 2010 14:55:20 GMT

← Older revision		Revision as of 14:55, 21 June 2010
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	http://www.xilinx.com/support/documentation/xc9500xl.htm		http://www.xilinx.com/support/documentation/xc9500xl.htm
-	~~=Reference Implementations=~~
-	~~==Monitor==~~
-	This monitor application uses the CPLD to watch events and trigger an alarm when a condition is reached. By delegating the monitoring task to the CPLD, the processor can concentrate on other tasks. If properly implemented, this distributed processing can lead to very efficient applications.
-	The event being monitored is the number of pulses on pin 30 (PXC7) of the extended I/O connector J12. It uses two CPLD registers: the current count (RXA) and the count limit (RXB). Once the count limit is reached, the interrupt line (IO_INTR) is asserted. A status of the count changes is printed on serial port COM1. The count changes are monitored every 100 ms. The alarm event is handled asynchronously using an interrupt service routine (ISR).
-	To run this application, download the monitor.svf firmware to the CPLD using the procedure in section 3 of the manual and the cpld_monitor.bin firmware to the microcontroller using a JTAG or the Luminary Flash Programmer.
-	~~==SPI Port Extender==~~
-	The SPI port extender application expands the available I/Os to the processor using both the extended I/O connector J12 and the PC/104 connector J13. The PC/104 signals are reclassified according to table 2-1.
-	~~[[Image:104 Connector Pin out.png\|center\|]]~~

Support at 14:54, 21 June 2010

Support — Mon, 21 Jun 2010 14:54:38 GMT

← Older revision		Revision as of 14:54, 21 June 2010
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	http://www.xilinx.com/support/documentation/xc9500xl.htm		http://www.xilinx.com/support/documentation/xc9500xl.htm
-	=Reference Implementations	+	=Reference Implementations=
	==Monitor==		==Monitor==
	This monitor application uses the CPLD to watch events and trigger an alarm when a condition is reached. By delegating the monitoring task to the CPLD, the processor can concentrate on other tasks. If properly implemented, this distributed processing can lead to very efficient applications.		This monitor application uses the CPLD to watch events and trigger an alarm when a condition is reached. By delegating the monitoring task to the CPLD, the processor can concentrate on other tasks. If properly implemented, this distributed processing can lead to very efficient applications.

Support: /* SPI Port Extender */

Support — Mon, 21 Jun 2010 14:54:06 GMT

SPI Port Extender

← Older revision		Revision as of 14:54, 21 June 2010
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	==SPI Port Extender==		==SPI Port Extender==
	The SPI port extender application expands the available I/Os to the processor using both the extended I/O connector J12 and the PC/104 connector J13. The PC/104 signals are reclassified according to table 2-1.		The SPI port extender application expands the available I/Os to the processor using both the extended I/O connector J12 and the PC/104 connector J13. The PC/104 signals are reclassified according to table 2-1.
-	[[Image:~~PC/~~104 Connector Pin out.png\|center\|]]	+	[[Image:104 Connector Pin out.png\|center\|]]

Support at 14:52, 21 June 2010

Support — Mon, 21 Jun 2010 14:52:44 GMT

← Older revision		Revision as of 14:52, 21 June 2010
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	http://www.xilinx.com/support/documentation/xc9500xl.htm		http://www.xilinx.com/support/documentation/xc9500xl.htm
		+	=Reference Implementations
		+	==Monitor==
		+	This monitor application uses the CPLD to watch events and trigger an alarm when a condition is reached. By delegating the monitoring task to the CPLD, the processor can concentrate on other tasks. If properly implemented, this distributed processing can lead to very efficient applications.
		+	The event being monitored is the number of pulses on pin 30 (PXC7) of the extended I/O connector J12. It uses two CPLD registers: the current count (RXA) and the count limit (RXB). Once the count limit is reached, the interrupt line (IO_INTR) is asserted. A status of the count changes is printed on serial port COM1. The count changes are monitored every 100 ms. The alarm event is handled asynchronously using an interrupt service routine (ISR).
		+	To run this application, download the monitor.svf firmware to the CPLD using the procedure in section 3 of the manual and the cpld_monitor.bin firmware to the microcontroller using a JTAG or the Luminary Flash Programmer.
		+	==SPI Port Extender==
		+	The SPI port extender application expands the available I/Os to the processor using both the extended I/O connector J12 and the PC/104 connector J13. The PC/104 signals are reclassified according to table 2-1.
		+	[[Image:PC/104 Connector Pin out.png\|center\|]]

Support at 14:49, 21 June 2010

Support — Mon, 21 Jun 2010 14:49:24 GMT

← Older revision		Revision as of 14:49, 21 June 2010
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	[[Image:CPLD_Table1.1.png\|center\|]]		[[Image:CPLD_Table1.1.png\|center\|]]
	The reference implementation uses an SSI (Synchronous Serial Interface) port at 4 MHz. The serial interface uses 9-bit frames including a 1-bit command flag and an 8-bit data word. (SSI). Up to 63 CPLD I/O pins in connectors J12 and J13 are available for applications.		The reference implementation uses an SSI (Synchronous Serial Interface) port at 4 MHz. The serial interface uses 9-bit frames including a 1-bit command flag and an 8-bit data word. (SSI). Up to 63 CPLD I/O pins in connectors J12 and J13 are available for applications.
		+	==Electrical Interface==
		+	The XC9572XL is a 3.3V device with 5V tolerant I/O. Please refer to the following Xilinx documents for guidelines on thresholds, termination and impedance.
		+
		+
		+	XC9572XL 3.3V High-Performance CPLD Data Sheet
		+
		+	http://www.xilinx.com/support/documentation/data_sheets/ds057.pdf
		+
		+
		+	Xilinx CPLD I/O User Guide
		+
		+	http://www.xilinx.com/support/documentation/user_guides/ug445.pdf
		+
		+
		+	XC9500XL CPLD Documentation
		+
		+	http://www.xilinx.com/support/documentation/xc9500xl.htm

Support: /* Processor Interface */

Support — Mon, 21 Jun 2010 14:48:12 GMT

Processor Interface

← Older revision		Revision as of 14:48, 21 June 2010
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	The ARM microcontroller uses 5 pins for communication with the CPLD as shown in Table 1-1.		The ARM microcontroller uses 5 pins for communication with the CPLD as shown in Table 1-1.
	[[Image:CPLD_Table1.1.png\|center\|]]		[[Image:CPLD_Table1.1.png\|center\|]]
		+	The reference implementation uses an SSI (Synchronous Serial Interface) port at 4 MHz. The serial interface uses 9-bit frames including a 1-bit command flag and an 8-bit data word. (SSI). Up to 63 CPLD I/O pins in connectors J12 and J13 are available for applications.

Support: Created page with 'TOC =Introduction= ==Expansion via Programmable Logic== The Eagle 100 includes a Xilinx XC9572XL Complex Programmable Logic Device(CPLD) that can augment the microcontroller …'

Support — Mon, 21 Jun 2010 14:46:25 GMT

Created page with '__TOC__ =Introduction= ==Expansion via Programmable Logic== The Eagle 100 includes a Xilinx XC9572XL Complex Programmable Logic Device(CPLD) that can augment the microcontroller …'

New page

__TOC__
=Introduction=
==Expansion via Programmable Logic==
The Eagle 100 includes a Xilinx XC9572XL Complex Programmable Logic Device(CPLD) that can augment the microcontroller capabilities using high speed logic. In this scenario, the CPLD can perform repetitive dedicated tasks and allow the processor to concentrate in more supervisory functions. Examples include event monitors, pwm generators, motor controllers and expansion bus interfaces. Micromint provides several reference implementations with source code that can be adapted to specific application requirements.
==Processor Interface==
The ARM microcontroller uses 5 pins for communication with the CPLD as shown in Table 1-1.
[[Image:CPLD_Table1.1.png|center|]]