Using CPLD/1
From Manuals
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The ARM microcontroller uses 5 pins for communication with the CPLD as shown in Table 1-1. | The ARM microcontroller uses 5 pins for communication with the CPLD as shown in Table 1-1. | ||
[[Image:CPLD_Table1.1.png|center|]] | [[Image:CPLD_Table1.1.png|center|]] | ||
| + | The reference implementation uses an SSI (Synchronous Serial Interface) port at 4 MHz. The serial interface uses 9-bit frames including a 1-bit command flag and an 8-bit data word. (SSI). Up to 63 CPLD I/O pins in connectors J12 and J13 are available for applications. | ||
Revision as of 14:48, 21 June 2010
Contents |
Introduction
Expansion via Programmable Logic
The Eagle 100 includes a Xilinx XC9572XL Complex Programmable Logic Device(CPLD) that can augment the microcontroller capabilities using high speed logic. In this scenario, the CPLD can perform repetitive dedicated tasks and allow the processor to concentrate in more supervisory functions. Examples include event monitors, pwm generators, motor controllers and expansion bus interfaces. Micromint provides several reference implementations with source code that can be adapted to specific application requirements.
Processor Interface
The ARM microcontroller uses 5 pins for communication with the CPLD as shown in Table 1-1.
The reference implementation uses an SSI (Synchronous Serial Interface) port at 4 MHz. The serial interface uses 9-bit frames including a 1-bit command flag and an 8-bit data word. (SSI). Up to 63 CPLD I/O pins in connectors J12 and J13 are available for applications.