Using CPLD/2
From Manuals
(Created page with '__TOC__ =Reference Implementations= ==Monitor== This monitor application uses the CPLD to watch events and trigger an alarm when a condition is reached. By delegating the monitor…') |
(→SPI Port Extender) |
||
| Line 8: | Line 8: | ||
The SPI port extender application expands the available I/Os to the processor using both the extended I/O connector J12 and the PC/104 connector J13. The PC/104 signals are reclassified according to table 2-1. | The SPI port extender application expands the available I/Os to the processor using both the extended I/O connector J12 and the PC/104 connector J13. The PC/104 signals are reclassified according to table 2-1. | ||
[[Image:104 Connector Pin out.png|center|]] | [[Image:104 Connector Pin out.png|center|]] | ||
| + | (*) Controlled by MCU, not CPLD firmware. | ||
| + | Table 2-1: PC/104 connector pin out for Extended I/O | ||
Revision as of 14:56, 21 June 2010
Contents |
Reference Implementations
Monitor
This monitor application uses the CPLD to watch events and trigger an alarm when a condition is reached. By delegating the monitoring task to the CPLD, the processor can concentrate on other tasks. If properly implemented, this distributed processing can lead to very efficient applications. The event being monitored is the number of pulses on pin 30 (PXC7) of the extended I/O connector J12. It uses two CPLD registers: the current count (RXA) and the count limit (RXB). Once the count limit is reached, the interrupt line (IO_INTR) is asserted. A status of the count changes is printed on serial port COM1. The count changes are monitored every 100 ms. The alarm event is handled asynchronously using an interrupt service routine (ISR). To run this application, download the monitor.svf firmware to the CPLD using the procedure in section 3 of the manual and the cpld_monitor.bin firmware to the microcontroller using a JTAG or the Luminary Flash Programmer.
SPI Port Extender
The SPI port extender application expands the available I/Os to the processor using both the extended I/O connector J12 and the PC/104 connector J13. The PC/104 signals are reclassified according to table 2-1.
(*) Controlled by MCU, not CPLD firmware. Table 2-1: PC/104 connector pin out for Extended I/O